Summary written by Jobs Hindustan from NXP Semiconductors' advert and our data on 8,417 current jobs in India. How we check every job
At a glance
NXP Semiconductors has an opening for PRINCIPAL PHYSICAL VERIFICATION ENGINEER in Bengaluru. It is a full-time role in Hardware & Semiconductors, first listed on 31 October. The description mentions CAD. NXP Semiconductors has 167 other openings in India, 85 of them in Bengaluru. Across all employers on Jobs Hindustan there are 215 Hardware & VLSI openings in Bengaluru today; the typical one asks for 7 years.
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Before you apply
- Check it is still open. We found this job on NXP Semiconductors' Workday site on 31 October 2026 and checked it again 4 November at 5:47 am IST. When an employer takes a job down, we remove it at our next daily update.
- Check the location works for you. This role is based in Bengaluru. If you would need to move, ask whether relocation support is offered.
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About hiring at NXP Semiconductors
NXP Semiconductors has 168 openings in India on Jobs Hindustan today across 5 cities. Most are in software & IT (80), hardware & VLSI (51) and data & AI (16). The biggest locations are Bengaluru (86), Noida (66) and Pune (26). 1% of them can be done from home, and 1% are open to freshers or interns. We collect NXP Semiconductors' jobs every day straight from its own careers system (Workday), never from job boards, agencies or consultants.
The employer's advert
This is NXP Semiconductors' own description of the job, copied word for word from its careers site. We have not edited it.
Show the full advert from NXP SemiconductorsHide the advert297 words
We are seeking a talented Physical Verification Design Engineer to join our VLSI design team. This role involves ownership of full-chip and block-level physical verification (PV) signoff, ensuring designs meet foundry and reliability requirements. The candidate will collaborate closely with physical design, PDK, CAD, and tapeout teams to deliver high-quality silicon.
Key Responsibilities
- Perform physical verification (PV) for block-level and full-chip designs, including:
- Design Rule Check (DRC)
- Layout Versus Schematic (LVS)
- Electrical Rule Check (ERC)
- Antenna, density, and reliability checks
- Drive signoff closure by identifying and resolving PV violations efficiently.
- Work with physical design and layout teams to debug and fix violations.
- Develop and maintain runsets, decks, and automation flows using industry-standard tools.
- Analyze foundry decks and PDK updates, ensuring compliance with process requirements.
- Lead tapeout readiness reviews and ensure high-quality database delivery.
- Perform hierarchical verification and regression management.
- Participate in improving verification methodologies, runtime, and capacity optimization.
- Interface with foundry and EDA vendors to resolve tool or deck-related issues.
- Mentor junior engineers and review their work as needed.
Preferred / Added Advantage Skills
- Exposure to Physical Design (PD) concepts, including:
- Floorplanning (macro placement, block shaping, congestion awareness)
- Power Delivery Network (PDN) design (power grid, IR drop considerations)
- Understanding of:
- Placement, CTS, routing flows
- PD-PV interaction and impact of layout decisions on DRC/LVS closure
- Knowledge of:
- EM/IR, latch-up, ESD reliability checks
- Multi-patterning / EUV constraints
- Experience with full-chip integration and SoC-level challenges
- Ability to correlate PV issues with PD root causes (e.g., spacing, density, routing hotspots)
- Exposure to flow automation and methodology development
Soft Skills
- Strong analytical and problem-solving ability
- Effective communication across cross-functional teams
- Ownership mindset with focus on quality and timelines
- Ability to work independently and guide team members
Jobs Hindustan copied this listing from NXP Semiconductors' official careers site on 30 October 2026 and checked it again 4 November at 5:47 am IST. NXP Semiconductors never asks candidates for money. If anyone does, it is a scam.
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