Summary written by Jobs Hindustan from NXP Semiconductors' advert and our data on 8,417 current jobs in India. How we check every job
At a glance
NXP Semiconductors has an opening for Senior Lead Engineer - STA in Noida. It is a full-time role in Software & IT, first listed on 31 October. NXP Semiconductors has 167 other openings in India, 65 of them in Noida. Across all employers on Jobs Hindustan there are 83 Software & IT openings in Noida today; the typical one asks for 8 years.
Before you apply
- Check it is still open. We found this job on NXP Semiconductors' Workday site on 31 October 2026 and checked it again 4 November at 5:47 am IST. When an employer takes a job down, we remove it at our next daily update.
- Check the location works for you. This role is based in Noida. If you would need to move, ask whether relocation support is offered.
- Know your notice period. If you are working now, recruiters will ask how soon you can join. Work out your last working day with our notice period calculator, and read our guide to notice periods and resigning.
- Understand any offer. The CTC in an offer letter is not what reaches your bank account each month. Our CTC to in-hand salary calculator gives a rough monthly figure, and our CTC guide explains each part.
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About hiring at NXP Semiconductors
NXP Semiconductors has 168 openings in India on Jobs Hindustan today across 5 cities. Most are in software & IT (80), hardware & VLSI (51) and data & AI (16). The biggest locations are Bengaluru (86), Noida (66) and Pune (26). 1% of them can be done from home, and 1% are open to freshers or interns. We collect NXP Semiconductors' jobs every day straight from its own careers system (Workday), never from job boards, agencies or consultants.
The employer's advert
This is NXP Semiconductors' own description of the job, copied word for word from its careers site. We have not edited it.
Show the full advert from NXP SemiconductorsHide the advert157 words
The Digital Physical Design Engineer is responsible for complete STA signoff for the SOC or Subsystem.
The individual is responsible for writing timing constraints, interacting with the counterpart functions, such as Frontend, DFT and IP to write correct constraints, refining constraints throughout SOC design cycle and constraints validation.
The individual must have exposure of AI and use AI in STA activities.
The individual is responsible for complete timing signoff till the tapeout for subsystem or full chip.
Must have leading capabilities on signoff function.
Must have worked on SDF generation and validation.
Must have all knowledge of SI closure.
Must have exposure to higher tech nodes such as 16nm and 5nm.
Must be conversant with physical design flows and functions and must possess good knowledge of placement, CTS and Routing.
The individual contributes to problem solving related to physical design. Contributes to define best Physical design strategy per technology node.
#LI-2734Jobs Hindustan copied this listing from NXP Semiconductors' official careers site on 30 October 2026 and checked it again 4 November at 5:47 am IST. NXP Semiconductors never asks candidates for money. If anyone does, it is a scam.
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